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EL5128
Data Sheet May 4, 2007 FN7000.3
Dual VCOM Amplifier & Gamma Reference Buffer
The EL5128 integrates two VCOM amplifiers with a single gamma reference buffer. Operating on supplies ranging from 5V to 15V, while consuming only 2.0mA, the EL5128 has a bandwidth of 12MHz (-3dB) and provides common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables the amplifier to offer maximum dynamic range at any supply voltage. The EL5128 also features fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). The EL5128 is targeted at TFT-LCD applications, including notebook panels, monitors, and LCD-TVs. It is available in the 10 Ld MSOP package and is specified for operation over the -40C to +85C temperature range.
Features
* Dual VCOM amplifier * Single gamma reference buffer * 12MHz -3dB bandwidth * Supply voltage = 4.5V to 16.5V * Low supply current = 2.0mA * High slew rate = 10V/s * Unity-gain stable * Beyond the rails input capability * Rail-to-rail output swing * Ultra-small package * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
EL5128 (10 LD MSOP) TOP VIEW
VOUTA 1 VINA- 2 VINA+ 3 VS+ 4 VINC 5 -+ +10 VOUTB 9 VINB8 VINB+ 7 VS6 VOUTC
Applications
* TFT-LCD drive circuits * Notebook displays * LCD desktop monitors * LCD-TVs
Ordering Information
PART NUMBER EL5128CY EL5128CY-T7 EL5128CY-T13 EL5128CYZ (Note) EL5128CYZ-T7 (Note) PART MARKING 2 2 2 BAAAA TAPE & REEL 7" 13" PACKAGE PKG. DWG. #
10 Ld MSOP MDP0043 (3.0mm) 10 Ld MSOP MDP0043 (3.0mm) 10 Ld MSOP MDP0043 (3.0mm) 10 Ld MSOP MDP0043 (3.0mm) (Pb-free) 10 Ld MSOP MDP0043 (3.0mm) (Pb-free) 10 Ld MSOP MDP0043 (3.0mm) (Pb-free)
BAAAA
7"
EL5128CYZ-T13 BAAAA (Note)
13"
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5128
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS + 0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . 30mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C
Thermal information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL AV
VS+ = +5V, VS- = -5V, RL = 10k and CL = 10pF to 0V, TA = +25C Unless Otherwise Specified CONDITION MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain Voltage Gain
VCM = 0V (Note 1) VCM = 0V
2 5 2 1 1.35
12
mV V/C
50
nA G pF
(VCOM amps) (VCOM amps) for VIN from -5.5V to +5.5V -4.5V VOUT +4.5V (VCOM amps) -4.5V VOUT +4.5V
-5.5 50 75 0.995 70 95
+5.5
V dB dB
1.005
V/V
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -5mA IL = 5mA 4.85 -4.92 4.92 120 30 -4.85 V V mA mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (per amplifier) VS is moved from 2.25V to 7.75V No load 60 80 660 1000 dB A
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS NOTES: 1. Measured over operating temperature range. 2. Slew rate is measured on rising and falling edges. Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation -4.0V VOUT +4.0V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF RL = 10k, CL = 10pF (VCOM amps) RL = 10k, CL = 10pF (VCOM amps) f = 5MHz 10 500 12 8 50 75 V/s ns MHz MHz dB
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FN7000.3 May 4, 2007
EL5128
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain Voltage Gain for VIN from -0.5V to +5.5V 0.5V VOUT + 4.5V 0.5V VOUT + 4.5V -0.5 45 75 0.995 66 95 1.005 VCM = 2.5V (Note 3) VCM = 2.5V 2 5 2 1 1.35 +5.5 50 10 mV V/C nA G pF V dB dB V/V VS+ = +5V, VS- = 0V, RL = 10k and CL = 10pF to 2.5V, TA = +25C Unless Otherwise Specified CONDITION MIN TYP MAX UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -5mA IL = +5mA 4.85 80 4.92 120 30 150 mV V mA mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (per amplifier) VS is moved from 4.5V to 15.5V No load 60 80 660 1000 dB A
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS NOTES: 3. Measured over operating temperature range. 4. Slew rate is measured on rising and falling edges. Slew Rate (Note 4) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation 1V VOUT 4V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF RL = 10k, CL = 10pF RL = 10k, CL = 10pF f = 5MHz 10 500 12 8 50 75 V/s ns MHz MHz dB
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FN7000.3 May 4, 2007
EL5128
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMIR CMRR AVOL AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Common-Mode Input Range Common-Mode Rejection Ratio Open-Loop Gain Voltage Gain for VIN from -0.5V to +15.5V 0.5V VOUT 14.5V 0.5V VOUT 14.5V -0.5 53 75 0.995 72 95 1.005 VCM = 7.5V (Note 5) VCM = 7.5V 2 5 2 1 1.35 +15.5 50 14 mV V/C nA G pF V dB dB V/V VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = +25C Unless Otherwise Specified CONDITION MIN TYP MAX UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short Circuit Current Output Current IL = -5mA IL = +5mA 14.85 80 14.92 120 30 150 mV V mA mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (per amplifier) VS is moved from 4.5V to 15.5V No load 60 80 660 1000 dB A
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS NOTES: 5. Measured over operating temperature range. 6. Slew rate is measured on rising and falling edges. Slew Rate (Note 6) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation 1V VOUT 14V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF RL = 10k, CL = 10pF RL = 10k, CL = 10pF f = 5MHz 10 500 12 8 50 75 V/s ns MHz MHz dB
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FN7000.3 May 4, 2007
EL5128 Typical Performance Curves
1800 QUANTITY (AMPLIFIERS) QUANTITY (AMPLIFIERS) VS=5V 1600 T =25C A 1400 1200 1000 800 600 400 200 0 -12 -10 -8 -6 -4 -2 -0 10 12 2 4 6 8 INPUT OFFSET VOLTAGE (mV) TYPICAL PRODUCTION DISTRIBUTION 70 VS=5V 60 50 40 30 20 10 0 13 15 17 19 INPUT OFFSET VOLTAGE DRIFT, TCVOS (V/C) 21 150 150
FN7000.3 May 4, 2007
TYPICAL PRODUCTION DISTRIBUTION
1
3
5
7
9
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
INPUT OFFSET VOLTAGE (mV)
10
VS=5V INPUT BIAS CURRENT (nA) 2.0
VS=5V
5
0.0
0
-5
-2.0 -50 0 50 100
-50
0
50
100
150
DIE TEMPERATURE (C)
DIE TEMPERATURE (C)
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
4.97 OUTPUT HIGH VOLTAGE (V) OUTPUT LOW VOLTAGE (V) VS=5V IOUT=5mA 4.96
-4.91 -4.92 -4.93 -4.94 -4.95 -4.96 -4.97 -50 0 50 100 150 -50 0 50 100 DIE TEMPERATURE (C) DIE TEMPERATURE (C) VS=5V IOUT=-5mA
4.95
4.94
4.93
FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
5
11
EL5128 Typical Performance Curves
(Continued)
100 OPEN-LOOP GAIN (dB)
VS=5V RL=10k SLEW RATE (V/s)
10.40
VS=5V
10.35
90
10.30
80
10.25
-50
0
50
100
150
-50
0
50
100
150
DIE TEMPERATURE (C)
DIE TEMPERATURE (C)
FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE
FIGURE 8. SLEW RATE vs TEMPERATURE
VS=5V SUPPLY CURRENT (mA) 0.55 SUPPLY CURRENT PER AMPLIFIER (A)
700 TA=25C 600
0.5
500
400
0.45 300 -50 0 50 100 150 0 5 10 15 20 DIE TEMPERATURE (C) SUPPLY VOLTAGE (V)
FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE
FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE
200 150 GAIN (dB) 100 50 GAIN 0 VS=5V, TA=25C RL=10k to GND CL=12pF to GND -50 10 100 1K 10K 100K 1M 10M
20 MAGNITUDE (NORMALIZED) (dB) -30 -80 -130 -180 -230 100M PHASE ()
5 10k 0 1k 560 -5 150
PHASE
-10
CL=10pF AV=1 VS=5V 1M 10M 100M
-15 100K
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS RL
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FN7000.3 May 4, 2007
EL5128 Typical Performance Curves
(Continued)
20 MAGNITUDE (NORMALIZED) (dB)
OUTPUT IMPEDANCE ()
RL=10k AV=1 10 VS=5V 12pF 0 50pF
200 160 120 80 40 0 10K AV=1 VS=5V TA=25C
-10 -20 1000pF -30 100K
100pF
1M
10M
100M
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 14. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY
12 MAXIMUM OUTPUT SWING (VP-P) 10
80
60 CMRR (dB) 8 6 4 2 VS=5V TA=25C AV=1 RL=10k CL=12pF DISTORTION <1% 100K 1M 10M
40
20 VS=5V TA=25C 1K 10K 100K 1M 10M
0 10K
0 100
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 16. CMRR vs FREQUENCY
80
PSRR+ PSRRVOLTAGE NOISE (nV/Hz)
600
60 PSRR (dB)
100
40
10
20 VS=5V TA=25C 1K 10K 100K 1M 10M
0 100
1 100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. PSRR vs FREQUENCY
FIGURE 18. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY
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FN7000.3 May 4, 2007
EL5128 Typical Performance Curves
(Continued)
0.010 0.009 0.008 X-TALK (dB) VS=5V RL=10k AV=1 VIN=1VRMS 10K FREQUENCY (Hz) 100K THD+ N (%) 0.007 0.006 0.005 0.004 0.003 0.002 0.001 1K
-60 MEASURED CHANNEL A TO B VS=5V R =10k -80 AL =1 V VIN=220mVRMS -100
-120
-140 1K
10K
100K FREQUENCY (Hz)
1M
6M
FIGURE 19. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
FIGURE 20. CHANNEL SEPARATION vs FREQUENCY RESPONSE
OVERSHOOT (%)
50 30 10 10 100 LOAD CAPACITANCE (pF) 1K
STEP SIZE (V)
V =5V 90 AS =1 V RL=10k VIN=50mV 70 T =25C A
4 VS=5V AV=1 3 RL=10k 2 CL=12pF TA=25C 1 0 -1 -2 -3 -4 0 200 400
0.1%
0.1%
600
800
SETTLING TIME (ns)
FIGURE 21. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
FIGURE 22. SETTLING TIME vs STEP SIZE
1V
1s
50mV
200ns
VS=5V TA=25C AV=1 RL=10k CL=12pF
VS=5V TA=25C AV=1 RL=10k CL=12pF
FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE
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FN7000.3 May 4, 2007
EL5128 Pin Descriptions
PIN NUMBER 1 PIN NAME VOUTA PIN FUNCTION Amplifier A Output
VS+
EQUIVALENT CIRCUIT
GND
VS-
CIRCUIT 1 2 VINAAmplifier A Inverting Input
VS+
VS-
CIRCUIT 2 3 4 5 6 7 8 9 10 VINA+ VS+ VINC VOUTC VSVINB+ VINBVOUTB Amplifier A Non-Inverting Input Positive Power Supply Amplifier C Amplifier C Output Negative Power Supply Amplifier B Non-Inverting Input Amplifier B Inverting Input Amplifier B Output (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 2)
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FN7000.3 May 4, 2007
EL5128 Applications Information
Product Description
The EL5128 voltage feedback amplifier/buffer combination is fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability, it is unity gain stable, and has low power consumption (500A per amplifier). These features make the EL5128 ideal for a wide range of general-purpose applications. Connected in voltage follower mode and driving a load of 10k and 12pF, the EL5128 has a -3dB bandwidth of 12MHz while maintaining a 10V/s slew rate. diodes placed in the input stage of the device begin to conduct and over-voltage damage could occur.
1V 100s
1V
Operating Voltage, Input, and Output
The EL5128 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5128 specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the amplifiers extends 500mV beyond the supply rails. The output swings of the EL5128 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 25 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P.
VS=5V AV=1 TA=25C VIN=10VP-P
VS=2.5V TA=25C AV=1 VIN=6VP-P
FIGURE 26. OPERATION WITH BEYOND-THE-RAILS INPUT
Short Circuit Current Limit
The EL5128 will limit the short circuit current to 120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds 30mA. This limit is set by the design of the internal metal interconnects.
Driving Capacitive Loads
The EL5128 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The amplifiers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain.
INPUT
Power Dissipation
With the high-output drive capability of the EL5128 amplifier, it is possible to exceed the 125C "absolute-maximum junction temperature" under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
OUTPUT
FIGURE 25. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
Output Phase Reversal
The EL5128 is immune to phase reversal as long as the input voltage is limited from (VS-) -0.5V to (VS+) +0.5V. Figure 26 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection
10
FN7000.3 May 4, 2007
EL5128
where: * TJMAX = Maximum junction temperature
POWER DISSIPATION (W) 0.6 0.5 486mW 0.4 0.3 0.2 0.1 0
JA JA =
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
* TAMAX= Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or:
P DMAX = i x [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ]
M SO P1 20 0 6 C C// W W
when sourcing, and:
P DMAX = i x [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ]
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 0.9 POWER DISSIPATION (W) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 870mW
M 11
JA =
when sinking. where: * VS = Total supply voltage * ISMAX = Maximum supply current per amplifier * VOUTi = Maximum output voltage of the application * ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figures 27 and 28 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves in Figures 27 and 28.
SO
5
0 C/ W
P1
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Power Supply Bypassing and Printed Circuit Board Layout
The EL5128 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1F ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7F tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used.
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FN7000.3 May 4, 2007
EL5128 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
E
E1
PIN #1 I.D.
A2 b c
B
1 (N/2)
D E E1
e C SEATING PLANE 0.10 C N LEADS b
H
e L L1 N
0.08 M C A B
L1 A c SEE DETAIL "X"
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN7000.3 May 4, 2007

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